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หัวข้อ: ช่วยแปลให้หน่อยครับ เริ่มหัวข้อโดย: bogie ที่ เมษายน 18, 2008, 03:02:51 pm [color=red]Soft start and standby[/color]
If HPLL2 is pulled to ground by resetting the register SOFTST, the horizontal output pulses, vertical output currents and B+ control driver pulses will be inhibited. This means that HDRV (pin 8), BDRV (pin 6), VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this state. If HPLL2 is pulled to ground by an external DC current, vertical output currents stay active while HDRV (pin 8) and BDRV (pin 6) are in floating state. In both cases the PLL2 and the frequency-locked loop are disabled, CLBL (pin 16) provides a continuous blanking signal and HUNLOCK (pin 17) is floating. This option can be used for soft start, protection and power-down modes. When the HPLL2 pin is released again, an automatic soft start sequence on the horizontal drive as well as on the B+ drive output will be performed (see Figs 24 and 25). A soft start can only be performed if the supply voltage for the IC is a minimum of 8.6 V. The soft start timing is determined by the filter capacitor at HPLL2 (pin 30), which is charged with a constant current during soft start. If the voltage at pin 30 (HPLL2) reaches 1.1 V, the vertical output currents are enabled. At 1.7 V the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty cycle is reached. The voltage at HPLL2 increases further and performs a soft start at BDRV (pin 6) as well. The voltage at HPLL2 continues to rise until HPLL2 enters its normal operating range. The internal charge current is now disabled. Finally PLL2 and the frequency-locked loop are activated. If both functions reach normal operation, HUNLOCK (pin 17) switches from the floating status to normal vertical blanking, and continuous blanking at CLBL (pin 16) is removed. Output stage for line drive pulses [HDRV (pin 8)] An open-collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0.3 V at 20 mA. To protect the line deflection transistor, the output stage is disabled (floating) for a low supply voltage at VCC (see Fig.23). The duty cycle of line drive pulses is slightly dependent on the actual horizontal frequency. This ensures optimum drive conditions over the whole frequency range. X-ray protection The X-ray protection input XRAY (pin 2) provides a voltage detector with a precise threshold. If the input voltage at XRAY exceeds this threshold level for a certain time then control bit SOFTST is reset, which switches the IC into protection mode. In this mode several pins are forced into defined states: HUNLOCK (pin 17) is floating The capacitor connected to HPLL2 (pin 30) is discharged Horizontal output stage (HDRV) is floating B+ control driver stage (BDRV) is floating Vertical output stages (VOUT1 and VOUT2) are floating CLBL provides a continuous blanking signal. There are two different methods of restarting the IC: 1. XSEL (pin 9) is open-circuit or connected to ground. The control bit SOFTST must be set to logic 1 via the I2C-bus. The IC then returns to normal operation via soft start. 2. XSEL (pin 9) is connected to VCC via an external resistor. The supply voltage of the IC must be switched off for a certain period of time before the IC can be restarted again using the standard power-on procedure. Vertical oscillator and amplitude control This stage is designed for fast stabilization of vertical |